In the semiconductor industry, there is a constant push to make devices (e.g. transistors) smaller and smaller. By making devices smaller, it is possible to fit more circuitry onto the same semiconductor real estate, which in turn makes it possible to manufacture denser and less expensive components. While smaller devices give rise to many advantages, they may also cause some problems. One of the potential problems is gate leakage. In larger MOS transistors, it is safe to assume that the oxide layer between the gate terminal and the substrate is sufficiently large that there is almost no tunneling current between the gate and source and the gate and drain. However, as transistors get smaller and smaller, this oxide layer diminishes, and at some point, the oxide layer will become so small that the tunneling current will no longer be negligible. This tunneling current, also referred to herein as gate leakage, can lead to operational problems.
To illustrate how gate leakage can adversely affect a memory, reference will be made to the sample memory 100 shown in FIG. 1A, in which memory cells 110 are arranged in rows and columns. As shown in FIG. 1A, each row of memory cells 110 is coupled to a corresponding wordline 104, and each column of memory cells 110 is coupled to a pair of complementary bit lines 130. The wordlines 104 enable the memory cells 110 to be accessed (for read or for write) one row at a time, and the bit lines 130 enable data to be read out of or written into the memory cells 110.
Each wordline 104 is driven by a wordline driver 102, which in turn is controlled by an address decoder 106. A wordline driver 102 may drive a wordline 104 to a first logic level (e.g. a logic 1) to enable the memory cells 110 coupled to that wordline 104 to be accessed, or it may drive the wordline 104 to a second logic level (e.g. a logic 0) to prevent the memory cells 110 coupled to that wordline 104 from being accessed. As shown in FIG. 1A, each memory cell 110 is coupled to a wordline 104 via a pair of pass transistors 120. It is these pass transistors 120 that are turned on and off by a wordline driver 102 to enable or disable access to the memory cells 110. When a wordline driver 102 drives a wordline 104 to the first logic level, the pass transistors 120 coupled to that wordline 104 are turned on, which enables data to be read from or written into that row of memory cells 110 (via the bit lines 130). Conversely, when a wordline driver 102 drives a wordline 104 to the second logic level, the pass transistors 120 coupled to that wordline are turned off, which prevents the memory cells 110 in that row from being accessed. When the wordline 104 is driven to the first logic level, the pass transistors 120 are said to be in “normal operational mode” (i.e. access mode). When the wordline 104 is driven to the second logic level, the pass transistors 120 are said to be in “standby mode” (i.e. non-access mode).
Ideally, once a wordline 104 has made a transition from one logic level to another, there should be no current flowing between the wordline 104 and the pass transistors 120. Put another way, the pass transistors 120 should act as open circuits. However, because of tunneling current (i.e. gate leakage), these pass transistors 120 do not behave as open circuits; rather, they draw current from, or drive current onto the wordline 104. This can lead to undesirable results.
To illustrate, suppose that wordline driver 102(1) has driven wordline 104(1) to logic 0 (at logic 0, the voltage on wordline 104(1) should ideally be at 0 volts). At this logic level, the pass transistors 120 coupled to wordline 104(1) should be turned off (i.e. should be in standby mode). Once wordline driver 102(1) has driven wordline 104(1) to logic 0, there should ideally be no current flowing between wordline 104(1) and the pass transistors 120 coupled to wordline 104(1). However, because of tunneling current from the source to the gate and from the drain to the gate of the pass transistors 120, there is some current flow. This current flow is shown in FIG. 1B, where current is depicted as flowing from the gate of each pass transistor 120 onto wordline 104(1). This current will encounter the line resistances RL of wordline 104(1) (for the sake of simplicity, it will be assumed that each segment of wordline 104(1) has the same line resistance of RL). Because of this current flow through the line resistance RL(1), the voltage at node N(1) will be slightly higher than the voltage (which will be presumed to be 0 volts) put out by wordline driver 104(1). Similarly, due to the current flow through the line resistance RL(2), the voltage at node N(2) will be slightly higher than the voltage at node N(1). Continuing this analysis through to node N(n), it will be clear that the voltage at node N(n) will be higher than the voltage at node N(n−1), which will be higher than the voltage at the preceding nodes. Thus, because of the tunneling current, the voltages at the various nodes will be higher than the ideal 0 volts, with the node N(n) (referred to as the outermost edge node) experiencing the highest voltage.
These elevated voltages cause the pass transistors 120 (especially those coupled to the outer edge nodes) to be partially turned on, which in turn causes the charge on the memory cells 110 to leak onto the bit lines 130. This leakage causes unnecessary power consumption. For a high capacity memory have a large number of memory cells, this additional power consumption can be significant. Since minimizing power consumption is a goal of most memories, this unnecessary power consumption during standby mode is a highly undesirable result.
Gate leakage also adversely affects a memory in normal operational mode. To illustrate, suppose that wordline driver 102(1) has driven wordline 104(1) to logic 1 (at logic 1, the voltage on wordline 104(1) should ideally be at a reference voltage Vdd). At this logic level, the pass transistors 120 coupled to wordline 104(1) should be turned on (i.e. should be in normal operational mode). Once wordline driver 102(1) has driven wordline 104(1) to logic 1, there should ideally be no current flowing between wordline 104(1) and the pass transistors 120 coupled to wordline 104(1). However, because of tunneling current from the gate to the substrate and from the gate to the source and drain of the pass transistors 120, there is some current flow. This current flow is shown in FIG. 1C, where current is depicted as flowing from wordline 104(1) to the gate of each pass transistor 120. This current will encounter the line resistances RL of wordline 104(1). Because of this current flow through the line resistance RL(1), the voltage at node N(1) will be slightly lower than the voltage (which will be presumed to be Vdd) put out by wordline driver 104(1). Similarly, due to the current flow through the line resistance RL(2), the voltage at node N(2) will be slightly lower than the voltage at node N(1). Continuing this analysis through to node N(n), it will be clear that the voltage at node N(n) will be lower than the voltage at node N(n−1), which will be lower than the voltage at the preceding nodes. Thus, because of the tunneling current, the voltages at the various nodes will be lower than the ideal Vdd, with the node N(n) experiencing the lowest voltage.
These lower voltages cause the pass transistors 120 (especially those coupled to the outer edge nodes) to not be fully turned on, which in turn reduces the drive of the pass transistors 120. This reduces the speed at which the memory cells 110 can be read or written, which in turn degrades the performance of the memory. If the speed is reduced too much, the memory may not even be usable (“weak bit” effect), which would reduce the memory yield (i.e. a higher percentage of the memory may have to be discarded as not meeting required specifications). In addition, the memory may suffer from the transient effect of bitline to wordline coupling. The memory cells 110 coupled to the outer edge nodes will be worst hit because the path to recovery is through the wordline driver 102(1) at the other end of the wordline 104(1). Furthermore, writability may be a problem for the memory cells 110 coupled to the outer edge nodes as the pass transistors 110 are less turned on.
Overall, the gate leakage problem is a potentially significant one that can lead to adverse consequences. As a result, a mechanism is needed to mitigate its effects.